CS 3853 Computer Architecture Chapter 3 Section 5 Loop Example



Instruction
Reservation
Station
Execution
Unit
Issue
Cycle
Ex Start
Cycle
Ex End
Cycle
Memory
Cycle
CDB
cycle
Write
dest
L.D    F0,0(R1) F0
ADD.DF4,F0,F2 F4
S.DF4,0(R1) 0(R1)
L.D    F6,-8(R1) F6
ADD.DF8,F6,F2 F8
S.DF8,-8(R1) -8(R1)
L.D    F10,-16(R1) F10
ADD.DF12,F10,F2 F12
S.DF12,-16(R1) -16(R1)
L.D    F14,-24(R1) F14
ADD.DF16,F14,F2 F16
S.DF16,-24(R1) -24(R1)
DADDUIR1,R1,#32 R1
BNER1,R2,loop