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CS 3853 Computer Architecture Recitation 4 Fall 2013

There will not be a quiz in this recitation.

Current Practice Problems
  1. For each of the following sequences of instructions, determine the number of stall cyles needed for execution, both with and without forwarding.
    1.    DADD  R1, R2, R3
         DSUB  R4, R1, R5
         AND   R6, R1, R7
         
    2.    LD    R1, 8(R2)
         DSUB  R4, R1, R5
         AND   R6, R7, R8
         
  2. Find a method (other than forwarding) of reducing the number of stalls in part b) of the above problem.
  3. This question is about the execution of the instruction DADD R1, R2, #5
    by the unpipelined machine shown in Figure C.21.
    Assume that before the instruction is executed, R1 = 9 and R2=13.
    You may also want to look at the instruction format shown at the beginning of these notes.
    A select input of 0 on a mux selects the top daa input, and a select input of 1 selects the bottom data input.
    1. What is the top input to the Registers register file?
    2. What is the second input (from the top) to the Registers register file?
    3. What is the third input (from the top) to the Registers register file?
    4. What is the fourth input (from the top) to the Registers register file?
    5. What value will be stored in the A register?
    6. What value will be stored in the B register?
    7. What value will be stored in the Imm register?
    8. Which input is selected in Mux A?
    9. Which input is selected in Mux B?
    10. What is stored in ALU output?
    11. What is stored in COND?
    12. Which input is selected for Mux C?
    13. Which input is selected for Mux D?
  4. This question is about the execution of the following sequence of instructions by the pipelined machine shown in Figure C.22.
    Assume that before the instructions are executed we have the following register values:
    RegisterR1R2R3R4R5R6R7R8R9
    Value131517192123252729
    Assume that the first instruction is fetched in cycle i and that no branch instructions are executed before these.
    You may also want to look at the instruction format shown at the beginning of these notes.
    A select input of 0 on a mux selects the top daa input, and a select input of 1 selects the bottom data input.
    DADD R1, R2, R3
    DSUB R4, R5, R6  /* R4 = R5 - R6 */
    AND  R7, R8, #40
    OR   R7, R8, R9
    
    1. Which stage is the DADD instruction in during cycle i+3?
    2. Which stage is the DSUB instruction in during cycle i+3?
    3. Which stage is the AND instruction in during cycle i+3?
    4. What are the values of the two ALU inputs during cycle i+3?
    5. What are the values of the two ALU inputs during cycle i+2?
    6. What are the values of the two ALU inputs during cycle i+4?
    7. What is the top input to the Registers register file (labeled IR6..10) during cycle i+3?
    8. What is the second input to the Registers register file (labeled IR11..15) during cycle i+3?
    9. What is the third input to the Registers register file (labeled MEM/WB.IR) during cycle i+4?

Practive Problems for Pipeline Timing
  1. Fill in the timing diagram showing the pipeline stages for each instruction for the standard 5-stage pipeline without forwarding:
      instruction cycle 1  cycle 2  cycle 3  cycle 4  cycle 5  cycle 6  cycle 7  cycle 8  cycle 9  cycle 10 
     LD   R1, 8(R2)      
     DSUB R4, R5, R6      
     AND  R7, R8, R9      

  2. Fill in the timing diagram showing the pipeline stages for each instruction for the standard 5-stage pipeline without forwarding:
      instruction cycle 1  cycle 2  cycle 3  cycle 4  cycle 5  cycle 6  cycle 7  cycle 8  cycle 9  cycle 10 
     LD   R1, 8(R2)      
     DSUB R4, R1, R2      
     AND  R5, R1, R7      

  3. Fill in the timing diagram showing the pipeline stages for each instruction for the standard 5-stage pipeline with forwarding:
      instruction cycle 1  cycle 2  cycle 3  cycle 4  cycle 5  cycle 6  cycle 7  cycle 8  cycle 9  cycle 10 
     LD   R1, 8(R2)      
     DSUB R4, R1, R2      
     AND  R5, R1, R7      

Practice Problems for Chapter 1
  1. If machine performance improves by 30% per year, by what percentage will it have improved after 50 years?
  2. If machine A is 40% faster than machine B and machine B is 70% faster than machine C, how much faster is machine A than C?
  3. If machine A is 40% faster than machine B and machine A is 80% faster than machine C, how much faster is machine B than C?
  4. If machine performance has improved by a factor of 5,000 over 20 years, at what percentage did it increase each year, assuming that each year had the same percentage increase?
  5. The MTTF for a new drive 2TB drive is 1,000,000 hours and a new 4TB drive is 600,000 hours. What is the MTTF for a system made up of 4 2TB drives and 2 4TB drives?
  6. The MTTF for a new drive 2TB drive is 1,000,000 hours and a new 4TB drive is 600,000 hours. Which 12 TB system has a better MTTF, one made up of 2TB drives, or one made up of 4TB drives?
  7. What is the speedup obtained by doubling the speed of integer instructions if integer instructions take up 60% of the time on the old design?
  8. What is the speedup obtained by doubling the speed of integer instructions if integer instructions take up 60% of the time on the new design?
  9. Machine A executes integer instructions 30% faster than machine B, but machine B executes floating point instructions 50% faster than machine A. On other instructions the machines are identical. Which machine will be faster and by how much when running a program that on machine A spends 40% of its time on integer instructions and 20% of its time on floating point instructions?
  10. By how much would the floating point unit need to be speeded up in order to get a speedup of 1.5 on a task that uses the floating point unit half of the time?