DADD R1, R2, R3 DSUB R4, R1, R5 AND R6, R1, R7
LD R1, 8(R2) DSUB R4, R1, R5 AND R6, R7, R8
Register | R1 | R2 | R3 | R4 | R5 | R6 | R7 | R8 | R9 |
Value | 13 | 15 | 17 | 19 | 21 | 23 | 25 | 27 | 29 |
DADD R1, R2, R3 DSUB R4, R5, R6 /* R4 = R5 - R6 */ AND R7, R8, #40 OR R7, R8, R9
instruction | cycle 1 | cycle 2 | cycle 3 | cycle 4 | cycle 5 | cycle 6 | cycle 7 | cycle 8 | cycle 9 | cycle 10 |
LD R1, 8(R2) | ||||||||||
DSUB R4, R5, R6 | ||||||||||
AND R7, R8, R9 |
instruction | cycle 1 | cycle 2 | cycle 3 | cycle 4 | cycle 5 | cycle 6 | cycle 7 | cycle 8 | cycle 9 | cycle 10 |
LD R1, 8(R2) | ||||||||||
DSUB R4, R1, R2 | ||||||||||
AND R5, R1, R7 |
instruction | cycle 1 | cycle 2 | cycle 3 | cycle 4 | cycle 5 | cycle 6 | cycle 7 | cycle 8 | cycle 9 | cycle 10 |
LD R1, 8(R2) | ||||||||||
DSUB R4, R1, R2 | ||||||||||
AND R5, R1, R7 |