There will be a quiz in this recitation.
It will be a closed book exam. You may not use a computer.
You may bring a calculator that can do add, subtract, multiply, divide, powers (y^x), and logs.
The quiz will consist of three questions and each problem is worth 3 points:

• 1 point for turning in the paper
• 2 points for showing some reasonable work
• 3 points for showing work and getting the correct answer

The quiz problems will be similar to the daily questions from Thursday, Week 9.

After turning in the quiz, start on the problems below.
The first problem is similar to what was discussed in class last week.
The other problems are review for the second midterm exam.

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1. The diagram shows the memory organization of a processor with a TLB and 2 levels of cache.
   The number of bits in each field is labeled with a lower case letter, a through r.
   Find the numeric values a-r. If the value cannot be determined from the information given, write ND.
   Assume the following:
   • Virtual addresses are 64 bits
   • Physical addresses are 42 bits
   • The page size is 32K
   • The TLB has 64 entries and is direct mapped
   • The L1 cache is direct mapped with a block size of 128 bytes.
   • The L2 cache is 8MB and 2-way set associative
   • the L1 and L2 caches use the same block size
2. Suppose a cache can be accessed in one cycle, the hit ratio is 98% and the miss penalty to 20 cycles. What is the average access time?
3. If main memory has an access time of 30 ns and a transfer rate of 10,000 MB/sec, how long does it take to access and transfer 64 consecutive bytes?
4. The standard MIPS 5-stage pipeline has a CPI of 1 when all memory accesses are cache hits. Loads and stores are 20% of al instructions, the miss rate is 2% and the miss penalty is 30 cycles. What is the CPI?

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5. A 64KB direct mapped cache has a block size of 128 bytes. How many bits of a 32-bit address are used for the block offset, index, and tag.
6. Repeat the above problem for a 2-way set associative cache.
7. Repeat the above problem for a fully associative cache.
8. What is the minimum number of bits per entry needed to implemented LRU for a fully associative 64 KB cache with a block size of 32 bytes?
9. What is the purpose of using a dirty bit in each entry of a write-through cache?
10. Which is better, a CPI of 1.21 with a clock cycles time of .4 ns, or a CPI of 1.32 with a clock cycle if .38 ns.? Explain.
11. A memory system uses 2 caches, an L1 cache with a hit rate of .95 and a hit time of .5 ns, and an L2 cache with a hit rate of .99 and a hit time of 1.3 ns. The main memory access time is 20 ns. First the L1 cache is checked. If a miss occurs the L2 cache is checked. A miss in the L2 cache causes an access to main memory. What is the effective memory access time?