CS 3853 Architecture Notes on Chapter 3

Read Section 3.4

3.4: Overcoming Data Hazards with Dynamic Scheduling

This is done by the complier
It is hard to do when basic blocks are small
Cannot predict how long an instruction will take in the presence of cache misses
It must be geared toward a particular microarchitecture
In the (good) old days, users were expected to compile their own copies of software
Today, most software comes shrink-wrapped

1) DIV.D   F0,F2,F4
2) ADD.D   F6,F0,F8
3) S.D.    F6,0(R1)
4) SUB.D   F8,F10,F14
5) MUL.D   F6,F10,F8

Tomasulo's Approach
Renaming is handled by reservation stations.

One or more for each type of operation: load, store, FP add, FP mult, etc.
Contains:
- the instruction
- buffered operand values if available
- otherwise, (a reference to the) reservation station producing the result
Fetches and buffers operands as soon as they are available
Only the last output updates the register file
Load and store reservation stations are just buffers containing data and addresses

Issue
- Get the next instruction
- If there is an available reservation station (RS), issue the instruction to that RS
- Enter the operand values into the RS, if available.
  For each operand that is not available, enter the RS it is coming from
- If the destination is a register, set that register status so that its value will be coming from this reservation station.
Execute
- If an operand becomes available, store in all RS's waiting for it.
- If all operands are ready and an execution unit is available, start execution, but
- No instruction can start execution until all branches that proceed it in program order have completed.
  (This is addressed in a later section.)
- Loads and stores are handled in program order.
Write Result
- Write result on CDB (common data bus)
- This is broadcast into all reservation stations (and possibly one register) that need it
- Only one value may be put on the CDB in a cycle

Figure 3.6 shows the basic structure of a MIPS floating point unit using Tomasulo's algorithm.

Activity: Tomasulo's Algorithm

Tomasulo's Approach
Example: Overview of Tomasulo's algorithm execution
Assume the following sequence of instructions:

1.  L.D.   F6,32(R2)
2.  L.D.   F2,44(R3)
3.  MUL.D  F0,F2,F4
4.  SUB.D  F8,F2,F6
5.  DIV.D  F10,F0,F6
6.  ADD.D  F6,F8,F2

Note that in order to start execution:

Tomasulo's Approach
Answer the following questions, each time starting with the original assumptions:

How would the results change if there were only one add reservation station? answer
How would the results change if there were 2 multiply functional units? answer
The last instruction modifies F6 before the previous instruction which uses F6 starts to execute. Is this a problem? answer
How would this change if the DIV.D instruction used F2 instead of F0? answer
How would this change if the DIV.D instruction used F2 instead of F0 and there were 2 multiply functional units? answer
The instruction
ADD.D F0,F4,F4
is executed at the end of this code. On what cycle does it complete? answer

Today's News: November 6, 2015
Assignment 3 available
Change in quiz grade calculation

How would this change if the second memory access is a cache miss with a miss penalty of 6 cycles? answer
How would this change if the second memory access is a cache miss with a miss penalty of 6 cycles and the DIV.D instruction used F4 instead of F0? answer
How would this change if the an fmul takes 5 cycles instead of 10? answer