Read Section 3.6

---

3.5: Hardware-Based Speculation

Limitations of dynamic scheduling

• Best used within basic blocks
• Basic blocks are often small
• Must delay execution of instructions until all branches are resolved

Ideas of hardware-based speculation:

• Use dynamic branch prediction to choose the instructions to execute
• Speculation to allow the execution of instructions before control dependencies are resolved
• CDB feeds reservation stations, but not registers or memory
• Save results in a reorder buffer and store in registers and memory in separate commit phase

Summary:

• Issue in order
• execute and store results in RS out of order, even during speculation
• commit (write to registers and memory) in order, only after branches are resolved

Recall precise exceptions:
pipeline can be stopped when an exception occurs and restarted so that:

• the instructions before the exception have an effect
• instructions after the exception do not have any effect

Tomasulo's algorithm does not support precise exceptions.
Consider the example from Section 3.2:

   L.D    F0,0(R1)
   DADDUI R1,R1,#8
   ADD.D  F4,F0,F2
   S.D    F4, 8(R1)

The DADDUI may complete before the L.D access memory.
If the L.D has a page fault and is restarted, it will access the wrong memory location.

With hardware-based speculation, the DADDUI would not commit (store its results in R1) before the L.D completes, but it would allow the result of the DADDUI to be stored in any reservation station that needs it.

Note:

• An instruction does not change the (ISA) machine state until it commits.
• delay exceptions until the commit phase

Figure 3.11 shows the floating point unit using speculation.
This comparison illustrates the difference between this and Tomasulo's algorithm.

Today's News: December 3

No news yet.

The Reorder Buffer (ROB) has 4 fields:

• instruction type, indicates the type of destination: branch (none), store (memory), ALU or load (register)
• destination (register number or memory address)
• value (value to be stored until it commits)
• ready (true when value is ready)

The Reservations Stations (RS) are as before, but now keep track of the destination ROB
Registers get their values from the ROB, not the CDB

Four steps of instruction execution:

1. Issue
   • Issue if both RS and ROB slots are available
   • RS stores operands or ROB entries that will contain the operands (Q fields contain ROB slot numbers)
   • RS stores the ROB slot number for the result.
   • Destination register stores the ROB entry producing result. Why?
2. Execute
   • RS's Monitor the CDB for needed operands.
   • Start execution when both operands and functional unit are available.
3. Write result
   • When result is available, write it to the CDB, tagged with the ROB entry number
   • It is stored in the ROB entry and all RS's waiting for it.
   • Free the RS for this instruction.
4. Commit
   1. Commit something other than a branch with incorrect prediction
      • occurs when instruction at head of ROB has its value available
      • update result:
        • register updated with result (normal commit)
        • memory updated on a store
        • successfully predicted branch: no update necessary
      • ROB entry freed
   2. Commit branch with incorrect prediction
      • Flush the ROB and RS's for all instructions that were issued after the branch
      • Restart execution at the correct successor of the branch

Figure 3.12 shows how the reorder buffer and reservation stations are used with speculative evaluation.
Here is an interactive coding form example.

---